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計算機結構
Computer Architecture
吳安宇   109下

課程概述
1. the basic concept of risc (reduced instruction set computer), compared with cisc (complex instruction set computer)
2. the assembly/machine language of the mips cpu
3. detailed cpu design:
instruction set, data path, control unit, arithmetic logic unit (alu),
techniques to enhance cpu performance, e.g., pipelining and hazard control
4. memory hierarchy:
cache (l1$, l2$, etc.): how to improve data/instruction access time for cpu?
virtual memory: how to handle program/data that is larger than your physical (main) memory?
5. i/o peripherals:
know more about i/o devices and networking devices
6. new trend of multi-core cpus (overview)

課程目標
learn basic mips/risc-v cpu architecture and memory hierarchy of computer system.

課程要求
待補

指定閱讀
待補

參考書目
1. david a. patterson, and john l. hennessy, “computer organization and design – the hardware/software interface”, 5th edition (asian edition), morgan kaufman publishers, inc., 2013.
2. (verilog coding, optional) “verilog hdl: digital design and modeling,” by j. cavanagh, crc press, 2007.

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