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數位系統設計
Digital System Design
吳安宇   109下
課程概述
digital system design introduction
fundamentals of hardware description language
logic design at register transfer level
logic design with behavior coding, design validation
synthesizable coding of verilog
coding style and verification tool
synthesis tool usage
complexity management and performance improvement
implementation project: mips processor
課程目標
basics:
basic overview of digital systems
front-end cell-based design flow, theory & practice
refinement and improvement issues for digital systems

presentation:
implementation project
peer competetion for advanced design features
oral presentation
課程要求
prerequisite:
switch circuits and logic designs
electronics

grading:
homework: 30% (hw1:5% hw2:5% hw3:10% hw4: 10%)
midterm exam: 30%
machine test: 5%
final project: 30%
impression: 5% (attendance/attitude)
指定閱讀
待補
參考書目
slides in courses are the main materials

related textbooks can be referred to:
“verilog hdl: digital design and modeling,” joseph cavanagh, crc press, 2007.
“computer organization and design: the hardware/software interface,” david a.
patterson and john l. hennessy, 2014, 5th edition.
“computer organization and design: the hardware/software interface,” david a.
patterson and john l. hennessy, risc-v edition.
“digital system designs and practices: using verilog hdl and fpgas," ming-bo lin,
wiley, 2008.
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