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邏輯合成與驗證
Logic Synthesis and Verification
江介宏   110上

課程概述
logic synthesis is an automated process of generating logic circuits satisfying certain boolean constraints and/or transforming logic circuits with respect to optimization objectives. it is an essential step in the design automation of vlsi systems and is crucial in extending the scalability of formal verification tools. this course introduces classic logic synthesis problems and solutions as well as some recent developments.

課程目標
this course is intended to introduce boolean algebra, boolean function representation and manipulation, logic circuit optimization, circuit timing analysis, formal verification, and other topics. the students may learn useful boolean reasoning techniques for various applications even beyond logic synthesis.

課程要求
the prerequisite is the undergrad "logic design" course. knowledge about data structures and programming would be helpful.

指定閱讀
待補

參考書目
* f. m. brown. boolean reasoning: the logic of boolean equations. dover, 2003.

* s. hassoun and t. sasao. logic synthesis and verification. springer, 2001.

* g. d. hachtel and f. somenzi. logic synthesis and verification algorithms. springer, 2006.

* w. kunz and d. stoffel. reasoning in boolean networks: logic synthesis and verification using testing techniques. springer, 1997.

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